1. Technical Field
The present invention relates to digital switching of a signal in a computer system. More specifically, the present invention relates to switching logical signals, or signals needed for controlling logic devices. Still more specifically, the present invention relates to a system and method for switching signals with clock logic devices without interfering with the logic of those devices.
2. Description of the Related Art
Digital switching of signals may be accomplished with a variety of devices. For example, digital multiplexers may have many different configurations, but in general, they have at least three inputs and a single output. On the input side, a generic multiplexer inputs a variety of data input signals. One signal is routed to the data output. Additionally, a generic multiplexer has another input for enabling a data input. This input causes an internal digital switch to change from one data input to another data input, thus routing the desired input to the output. A generic multiplexer switch data inputs without regard to the frequency, phase or sequence of the data steam on the data inputs.
Logic controlled devices are generally clocked by a digital clock but may, under certain circumstance, use an analog clock. Digital clocks such as crystal oscillators are generally considered superior to analog clocks because of their stability and reliability. Analog clocks, on the other hand, generally require tweaking the output frequency from time to time, which may upset the oscillation of the clock causing it to stop for a number of periods and go through a re-start sequence. While many logic controlled devices may remain stable during a set number of dead periods where the clock has become inoperable, many do not respond well to extremely short cycles between clock pulses or clocks. Such short cycling, or xe2x80x9cglitchingxe2x80x9d, may cause the logic device to lock up because certain components within the device respond to both clocks while other components within the device only respond to the first clock of a short cycle. Generally the device must be reset and re-started in order to clear the logic. Therefore, logic devices that rely on an analog clock for timing are at the mercy of the quirks of the analog technology even though digital clock pulses may be available from another clock.
A similar problem can occur when switching from one clock to another. When a generic multiplexer is used to switch from one clock to another, the multiplexer has no concept of timing and may output two pulses in rapid succession, one from the first clock and the second from the second clock after the switch. Thus, a glitch may cause logic controlled devices to lock up as described above. Therefore, if a circumstance arises for a logic controlled device to switch clocks, the switching process itself may lock up the logic device relying on the clock. Therefore, it would be advantageous to have an improved method and apparatus for switching between two clocks.
The present invention relates to a system and method for glitchlessly switching between one clock output and another clock output. Upon receiving a normal select signal to switch from one clock to another, the present invention continues to route the first clock to the output for a number of clock periods, as taken from the most reliable clock available, usually the crystal clock, whether that is the first or second clock. This is accomplished by accepting the normal select signal as a disconnect control signal only at the next positive edge of the first clock, delaying the disconnect signal for a number of cycles and then applying the disconnect signal to the control gate of the first clock only when a negative edge of the first clock is detected. This causes the first clock to disconnect from the output only at a negative edge. The edge designations could be reversed. Once the disconnect control signal has been issued and the first clock output is dead, the disconnect control signal starts the sequence for connecting the second clock to the output, thus the disconnect signal becomes the connect signal. In a manner similar to that described above, the connect control signal is accepted at the next positive edge of the second clock, delaying the connect signal for a number of cycles and then applying the connect signal to the control of the second clock only when a negative edge of the second clock is detected. This causes the second clock to disconnect from the output only at a negative edge. The edge designations could again be reversed. Additionally, the present invention automatically detects the failure of a specific clock by detecting a pulse edge and then counting clock periods of a second clock until detecting a second pulse edge. Upon detecting the second edge before a predetermined number of second clock cycles, the sequence resets and counting starts anew. If a predetermined number of second clock cycles are counted before the next edge is detected, a forced select signal is generated. Unlike the sequence described above, the forced selected signal clears the disconnect circuitry and is simultaneously applied directly to the disconnect gate of the first clock. The sequence then proceeds as described above. Clearly, the present invention may have more than two clock inputs.